Application-Specific Processor

As part of COMP3211 (Computer Architecture at UNSW) I worked with a small team to build an ASP in Verilog. The purpose of the ASP was to provide double-layer protection between a network and processor system.

We built a 4-stage pipelined processor with a 16-bit instruction set and verified its functionality through simulation in Vivado.

A schematic of the ASP